1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method therefor. In particular, the invention relates to a semiconductor device having plural semiconductor chips and a manufacturing method therefor.
2. Description of Related Art
To keep up with recent tendencies to downsize an electronic device, there is an increasing demand to package semiconductor chips with high density or high integration degree. To that end, a multi-chip module prepared by integrating plural semiconductor chips into one package has bee developed (see Japanese Unexamined Patent Publication Nos. 2003-273314, 2000-68316, and 2000-114452, for example).
In general, the multi-chip module has plural semiconductor chips on a lead frame that are obtained by arbitrarily connecting transistors, resistors or such other elements to compose a circuit. FIG. 5 is a schematic diagram showing the structure of a conventional multi-chip module 10 where two semiconductor chips 12 are mounted on the same lead frame 11. As shown in FIG. 5, the semiconductor chips 12 are connected face up on the island of the lead frame 11 via the die mounting member 13. Formed on each of the semiconductor chips 12 are circuit wiring lines 14 and a bonding pad 15. The bonding pads 15 on the respective chips are connected with each other via a bonding wire 16.
Incidentally, in the aforementioned multi-chip module 10, the bonding pads 15 for bonding the semiconductor chips 12 through the bonding wire 16 are formed with the thickness enough to suppress damage on the semiconductor chips, for the purpose of minimizing damage on the semiconductor chips upon the bonding.
Along with recent high-density integration of semiconductor chips, there is a need to reduce a pitch of the circuit wiring lines 14, and to reduce the thickness of each circuit wiring line 14 for realizing a processing with high dimensional accuracy. However, the circuit wiring line 14 and the bonding pad 15 are formed at the same time, so if the bonding pad 15 is thick, the circuit wiring line 14 is accordingly thick. Thus, it is difficult to reduce a pitch of the circuit wiring lines 14, and to downsize the semiconductor chips 12. In addition, in the case of etching only the circuit wiring line 14, an additional step of increasing the thickness of the bonding pad 15 is required, which costs high.